#ChipScope Core Inserter Project File Version 3.0
#Sun Sep 16 13:17:07 EDT 2018
Project.device.designInputFile=C\:\\Users\\Wenting\\Desktop\\Dramite\\fpga\\ml505\\Dramite\\top_cs.ngc
Project.device.designOutputFile=C\:\\Users\\Wenting\\Desktop\\Dramite\\fpga\\ml505\\Dramite\\top_cs.ngc
Project.device.deviceFamily=14
Project.device.enableRPMs=true
Project.device.outputDirectory=C\:\\Users\\Wenting\\Desktop\\Dramite\\fpga\\ml505\\Dramite\\_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=rst
Project.filter<10>=*d_wr*
Project.filter<11>=*d_rd*
Project.filter<12>=*d*
Project.filter<13>=*ble*
Project.filter<14>=*bhe*
Project.filter<15>=*cpu_bhe*
Project.filter<16>=*cpu_a*
Project.filter<17>=*rst*
Project.filter<18>=*clk*
Project.filter<1>=gnd
Project.filter<2>=
Project.filter<3>=*_a*
Project.filter<4>=*enable*
Project.filter<5>=*valid*
Project.filter<6>=*rom*
Project.filter<7>=*state*
Project.filter<8>=*cpu_*
Project.filter<9>=*_n*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_50
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=CPU_A_1_IBUF
Project.unit<0>.dataChannel<10>=CPU_A_11_IBUF
Project.unit<0>.dataChannel<11>=CPU_A_12_IBUF
Project.unit<0>.dataChannel<12>=CPU_A_13_IBUF
Project.unit<0>.dataChannel<13>=CPU_A_14_IBUF
Project.unit<0>.dataChannel<14>=rst
Project.unit<0>.dataChannel<15>=CPU_A_16_IBUF
Project.unit<0>.dataChannel<16>=CPU_A_17_IBUF
Project.unit<0>.dataChannel<17>=CPU_A_18_IBUF
Project.unit<0>.dataChannel<18>=CPU_A_19_IBUF
Project.unit<0>.dataChannel<19>=CPU_A_20_IBUF
Project.unit<0>.dataChannel<1>=CPU_A_2_IBUF
Project.unit<0>.dataChannel<20>=CPU_A_21_IBUF
Project.unit<0>.dataChannel<21>=CPU_A_22_IBUF
Project.unit<0>.dataChannel<22>=CPU_A_23_IBUF
Project.unit<0>.dataChannel<23>=CPU_ADS_B_IBUF
Project.unit<0>.dataChannel<24>=busmaster/cpu_d_wr<0>
Project.unit<0>.dataChannel<25>=busmaster/cpu_d_wr<1>
Project.unit<0>.dataChannel<26>=busmaster/cpu_d_wr<2>
Project.unit<0>.dataChannel<27>=busmaster/cpu_d_wr<3>
Project.unit<0>.dataChannel<28>=busmaster/cpu_d_wr<4>
Project.unit<0>.dataChannel<29>=busmaster/cpu_d_wr<5>
Project.unit<0>.dataChannel<2>=CPU_A_3_IBUF
Project.unit<0>.dataChannel<30>=busmaster/cpu_d_wr<6>
Project.unit<0>.dataChannel<31>=busmaster/cpu_d_wr<7>
Project.unit<0>.dataChannel<32>=busmaster/cpu_d_wr<8>
Project.unit<0>.dataChannel<33>=busmaster/cpu_d_wr<9>
Project.unit<0>.dataChannel<34>=busmaster/cpu_d_wr<10>
Project.unit<0>.dataChannel<35>=busmaster/cpu_d_wr<11>
Project.unit<0>.dataChannel<36>=busmaster/cpu_d_wr<12>
Project.unit<0>.dataChannel<37>=busmaster/cpu_d_wr<13>
Project.unit<0>.dataChannel<38>=busmaster/cpu_d_wr<14>
Project.unit<0>.dataChannel<39>=busmaster/cpu_d_wr<15>
Project.unit<0>.dataChannel<3>=CPU_A_4_IBUF
Project.unit<0>.dataChannel<40>=busmaster/cpu_ready_n
Project.unit<0>.dataChannel<41>=busmaster/cpu_d_dir
Project.unit<0>.dataChannel<42>=CPU_WR_IBUF
Project.unit<0>.dataChannel<43>=CPU_MIO_IBUF
Project.unit<0>.dataChannel<4>=CPU_A_5_IBUF
Project.unit<0>.dataChannel<5>=CPU_A_6_IBUF
Project.unit<0>.dataChannel<6>=CPU_A_7_IBUF
Project.unit<0>.dataChannel<7>=CPU_A_8_IBUF
Project.unit<0>.dataChannel<8>=CPU_A_9_IBUF
Project.unit<0>.dataChannel<9>=CPU_A_10_IBUF
Project.unit<0>.dataDepth=1024
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=44
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=rst
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=0
Project.unit<0>.type=ilapro
